This invention pertains to a liquid crystal display device, driving methods for liquid crystal display devices, inspection methods for electrical properties of liquid crystal display devices; and, in particular, liquid crystal display devices such as those in which transistors are formed on a liquid crystal matrix substrate for the purpose of driving a liquid crystal matrix.
In an active matrix liquid crystal display device is using thin film transistors (abbreviated as TFTs in the remainder of this document) as the switching elements, if it is possible to form the active matrix driving circuits from TFTs and fabricate those TFTs at the same time as the picture element (pixel) TFTs on the active matrix substrate, the need to provide driver integrated circuits (ICs) is removed; and this is convenient.
Compared to transistors integrated on single crystal silicon, however, the operating speeds of TFTs are slow and there is a definite limit to the increase in driving circuit speed attainable. Additionally, if the driving circuits are made to operate at high speeds, the power consumption will increase by that much more.
As examples of technology for operating driving circuits of liquid crystal display devices at high speed, there is the technology in Japanese Unexamined Patent Application Showa 61-32093 and the technology in pages 609-612 of the SID Digest (1992).
In the technology described in Japanese Unexamined Patent Application Showa 61-32093, the driving circuits are composed of multiple shift registers and, by driving each shift register by clocks with slightly different phases, the effective operating frequency of the shift registers is increased.
In the SID Digest (1992), pages 609-612, technology in which multiple analog switches are driven collectively by a single output of a timing control circuit and the video signal is written in parallel is shown.
As examples of technology striving for reduced power consumption in driving circuits, there is the technology contained in Japanese Unexamined Patent Application Showa 61-32093. This technology achieves reduced power consumption by dividing the driving circuits into multiple blocks and operating only blocks which must be used while keeping all other blocks out of operation.
When actually implementing the technology described in Japanese Unexamined Patent Application 61-32093, however, it is necessary to provide multiple clocks with differing phases which leads to increased complexity of the circuit configurations and an increase in the number of terminals.
Further, in the technology described in the SID Digest (1992), pages 609-612, because multiple analog switches are driven collectively, the load is heavy and it is necessary to provide a buffer which can drive a heavy load. Additionally, because of delays in the driving signals, it is easy for deviations to occur in the driving timing of each analog switch.
In the technology of Japanese Unexamined Patent Application 61-32093, a control circuit is necessary in order to selectively operate the divided blocks; and this leads to increased complexity of the circuitry. Additionally, this technology does not contribute at all to increasing the speed of the driving circuits.
Furthermore, when the driving circuits of the prior art described above are composed of TFTs, the circuits become complex in all cases; and the accurate, fast inspection of the circuits"" electrical characteristics is difficult such that there are problems in the evaluation of reliability.
The present invention has taken the problems of the prior art described above into consideration. The purpose is to provide a novel liquid crystal display device and associated driving methods which allow high speed operation, a certain degree of reduction in power consumption, and ease of inspection.
In one mode of the liquid crystal display device of the present invention, multiple pulses are generated simultaneously using a single shift register.
Consequently, the frequency of the shift register output signal can be increased without changing the frequency of the shift register operation clock. When the number of simultaneously generated pulses is N (N is natural number of two or greater), the frequency of the output signal of the shift register becomes N-times.
If the shift register output signal mentioned above is used to determine the sampling timing of the video signal in an analog driver, high speed data line driving can be realized. Also, if the shift register output signal mentioned above is used to determine the latch timing of the video signal in a digital driver, high speed latching of the video signal can be realized. Consequently, high speed operation of the driving circuits is possible without increasing power consumption even when the driving circuits of the liquid crystal matrix are composed of TFTs.
In the simultaneous generation of multiple pulses using a single shift register, it is good if a stationary state such as that obtained when, for example, a single same-polarity pulse is input to the shift register input terminal after one horizontal period of the video signal, waiting for the passage of at least (Nxe2x88x921) horizontal periods and N mutually spaced, parallel pulses are output from the output terminals of each stage of the shift register.
In another mode of the liquid crystal display device of the present invention, gate circuits are added to the single shift register with the output signals of the shift register input to the gate circuits, and the output signals of the gate circuits used as timing control signals of the circuits comprising the data line driving circuits. For example, the output signals of the gate circuits can be used as timing signals to determine the sampling timing of the video signal in an analog driver and can be used as timing signals to determine the latch timing of the video signal in a digital driver.
For example, if an EXCLUSIVE-OR gate is used as the gate circuit and the output of adjacent stages of the shift register are input into the EXCLUSIVE-OR gate, and a clock which makes two horizontal periods of the video signal one period is input to the shift register, the number of clock level changes in one horizontal period are reduced and further reduction in power consumption is possible.
In another mode of the liquid crystal display device of the present invention, by making the most use of a single shift register, a configuration which can perform electrical inspection of a liquid crystal matrix is achieved. For example, an input circuit for a testing signal is connected to one end of the data lines and video signal input lines are connected to the other ends of the data lines through analog switches.
Using the inspection signal input circuit, the inspection signals are input collectively to the data lines. Maintaining such an input, single pulses are output successively from the single shift register and these pulses are used to successively turn on multiple analog switches. The electrical characteristics of the data lines and analog switches can be inspected by receiving the inspection signals sent from one end of said data lines by way of the analog switches and the video signal input lines. For example, it is possible to accurately and quickly detect such things as frequency characteristics of data lines and analog switches as well as data line open circuits.